### Try playing with Sipeed Tang Nano (Linux version)

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Try playing with Sipeed Tang Nano (Linux version)

### Overview

FPGA board that LittleBee series FPGA of GOWIN rests Tang Nanoso came out from Sipeed, lists the contents tried from established a development environment on Linux until the L Chica.

### Installation of the development environment

Basically, the installation procedure of Sipeed Tang Nano of the Get Started page is written in it, Linux version at the moment is located in the TODO. Since the time being can be DL development environment binaries for Linux, I tried to properly put.

Tang Nano publications are http://dl.sipeed.com/TANG/Nano You can DL from.

1. http://dl.sipeed.com/TANG/Nano/IDE in the download_link.txtas described in, http://www.gowinsemi.com.cn/faq.aspx open a page of
2. 云源软件 for Linux(V1.9.2.01Beta) Choose to download the Linux version of the IDE.
3. To expand the archive of tar.gz format that you downloaded. In this case, since the archive does not contain the top-level directory, be deployed in it to make the appropriate directory.

mkdir gowin
tar xf Gowin_V1.9.2.01Beta_linux.tar.gz -C gowin

4. For the license server configuration, set the following environment variable. If you are using other flexlm system license, the existing LM_LICENSE_FILEtwo :to add, separated by. To be automatically set at the time of restart .bashrcmay want to add to per

export LM_LICENSE_FILE=27020@45.33.107.56

5. IDE/gw_ideTo run. Since it is said Toka license error, Use Floating License Serverselect, Serverto 45.33.107.56, Porttwo 10559by entering the Savepress, again gw_ideto run.

6. GOWIN FPGA Designer Success When the screen is displayed

This is the end the installation of the development environment in Linux.

### L to Chika

Color LED on and connect to the USB port I bought board will be on.

Try to change the lighting pattern for the operation check.

### Create Project

Sample project has are available, but you try to make the project with appropriate reading circuit diagrams.

Circuit diagram http://dl.sipeed.com/TANG/Nano/HDK located under the.

GOWIN FPGA DesignerThe top screen of the Quick Startcolor New Projectyou select.

In the dialog that appears FPGA Design Project, select the OKpress.

Project WizardSince There is displayed, as the destination of the path of the project Create in:and enter the path to the appropriate directory.

Name:To do this, enter the name of the project. Here suitably it is blinkerleft as an even.

After you enter Nextpress.

Select DeviceSince the screen is displayed, Seriesin GW1Nselect, from the table below GW1N-LV1QN48C6to select the.

SummarySince the screen is displayed, Finishpress.

Now that you have a project and add the necessary files.

DesignRight-click in the pane New Fileto select a.

It displayed Newin the dialog Verilog Fileto select the OKpress.

New VerilogA dialog box is displayed, Nametwo blinkby entering the OKpress.

blink.v Since but in a state that has been opened in the editor, and save it to copy and paste the code below.

clockA negative logic resetnreceives an input, a color LED R, G, This circuit outputs a signal corresponding to the B.

According to the data sheet of the Tang Nano 24[MHz]because the outgoing circuit of is mounted on the board, the outgoing circuit clockto the input of.

In addition, since the on the board has a push button of the active row is equipped with two, one of them resetnand to the input of the.

In the internal dividercounter of 24bit width named, that 2^24-1 = 16,777,215has a counter that can count up, the clock in this counter DIVIDER_UPPER = 1200000 - 1counts up. Therefore, dividerthe 1200000/24[MHz] = 1200000/2400000 = 0.5[s]returns to 0 every time.

dividerThere in the previous cycle back to 0 led_outby adding the value of one, it changes the LED lighting pattern for each 0.5 [s].

The LED lighting pattern of a total of 8 patterns will be repeated in order.

moduleblink(inputwireclock,inputwireresetn,outputwireled_r,outputwireled_g,outputwireled_b);

reg[23:0]divider;reg[2:0]led_out;localparam[23:0]DIVIDER_UPPER=24'd12_000_000-24'd1;

assignled_r=!led_out[0];assignled_g=!led_out[1];assignled_b=!led_out[2];

always@(posedgeclock)beginif(!resetn)begindivider<=0;led_out<=0;endelsebegindivider<=divider==DIVIDER_UPPER?0:divider+1;led_out<=divider==DIVIDER_UPPER?led_out+1:led_out;endend

endmodule


### Additional Synthesis and IO constraints

To add the IO constraints here, we once performed a synthesis.

In the right pane, Processopen the tab, Synthesizeand double-click.

When you double-click, Synthesizeyou place an arrow on the left side of the icon of the round and round rotation. Upon completion of the synthesis, it will be on the screen screen as shown below.

After completion of the synthesis, Processin the tab FloorPlannerand double-click.

FloorPlannerAt the time of the first run because there is no IO constraints file (* .cst), so you will see a dialog asking if you want to create a new, OKand press.

FloorPlanner is has become a screen, such as the following immediately after start-up.

Because this time you want to add the IO constraints, in the upper right corner of the pane Package Viewto open the tab, in the lower pane I/O Constraintsto open the tab.

Currently, each input and output port of the synthesized logic circuit because not assigned to the pins of the FPGA, and assign the pin while looking at the circuit diagram of the Tang Nano.

To assign a pin, I/O Constraintsselect the port that you want to assign a tab, Locationa cell in the column Package Viewand then drag and drop the pin that you want to assign that is displayed in.

Pin assignments for each port is as follows.

Port
Location
Remarks

clock
35
CH552 and shared signal of 24MHz crystal oscillator

resetn
15
button A (active low)

led_r
18
color LED red (active low)

led_g
16
color LED green (active low)

led_b
17
color LED blue (active low)

From the circuit diagram, the power supply voltage of the IO bank belonging of each pin is made to 3.3V, IO Typethe column LVCMOS33will change to.

Set to close the FloorPlanner Save When you are finished.

Although not required, add the timing constraints as prima facie perform the timing analysis.

From the Process tab Timing Constraints Editorand double-click.

Since the constraint file (* .sdc) or be sure to create a new because there is no in the same manner as in the case of IO constraints, select the OK.

Gowin Timing Constraints EditorSince There is displayed, right-click in the right-hand side of the screen, Create Clockselect the.

Create ClockA dialog box is displayed, Clock nameto clock, Frequencyto 24enter the [MHz].

ObjectsNext to the ...Press Select Objectsto display the dialog.

CollectionIn get_ports, Filtertwo *in the state in which you enter the Searchpress of a button. Matches&SelectedSince the port list is displayed in the list, clockselect the >press. Then, OKpress the Select Objectsclose the dialog.

Create ClockWhen you return to the dialog, Objectstwo [get_ports {clock}]because is input, OKand then press.

Save and close the Timing Constraints Editor.

### Generation of placement and routing the bit stream

In the Process pane Place & Routeand double-click. It ends the place-and-route after a while.

Place & Route ReportWhen you double-click the, place-and-route results report is displayed.

Timing Analysis ReportWhen you double-click a, you will see the timing analysis results. Anyway timing constraint violations seems not.

### Writing of the bit stream

Since the finished make a bit stream to write to the board, will try to move to write to actually board. Permanent configuration steps to Flash is a tutorial has been given, however, and configuration to the time being SRAM for the experiment. (To return to the original and turn off the power)

Do I have to note here, in order to write that requires administrator rights, it is to start the Programmer manually.

Programmer/bin/programmerStart with the administrator.

sudo Programmer/bin/programmer


Start Once you right-click Configure Deviceto select a.

Device configurationA dialog box is displayed, Access Modein SRAM Mode, Operationin SRAM Programto select a.

In addition, Programming Optionsof File namethe right ...Press to
(プロジェクトのディレクトリ)/impl/pnr/blinker.fsselect the.

SaveThe close the Device configuration dialog press, further from the right-click menu Program/Configureand choose, will begin writing of the bit stream.

### So that can also be used by the general user a Programmer

Create the following file.

/etc/udev/rules.d/50-tang-nano.rules
SUBSYSTEMS=="usb", ATTRS{idVendor}=="0403", ATTRS{idProduct}=="6010", ATTRS{product}=="Sipeed-Debug", GROUP="users", MODE="0666"


And then reload the configuration of udev.

sudo udevadm control --reload


Remove the Tang Nano from the USB port and reconnect.

Then, ftdi_sioto unload the driver.

sudo modprobe -r ftdi_sio


This will also be able to access the Tang Nano in the general user.

Try running the command-line version Programmer to try.

\$ Programmer/bin/programmer_cli --channel 0 --device GW1N-1 --operation_index 0
"Read Device Codes" starting on device-1...
ID code is: 0x0900281B
User code is: 0x00004951
Status code is: 0x0001F020
Cost 1.04 second(s)